MSM6779 ? semiconductor 1/9 general description the MSM6779 is a lcd dot matrix segment driver. fabricated in cmos technology, the device consists of 160-bit latches i and ii, a 160-bit level shifter, and a 4-level driver. the MSM6779 latches the 4-bit parallel display data sent from a microcontroller or a lcd controller to generate a lcd driving signal. this MSM6779 has a power-save function that sets all the drivers except one to the low supply current status (i dd sby). this driver's 3v-operation allows significant reduction in current consumption, suitable for battery-driving. the bias voltage to specify a drive level can be supplied externally. the MSM6779 can be used for various types of lcd panels. features ? logic supply voltage : 2.7 v to 5.5 v ? lcd drive voltage : a wide range from 14 v to 28 v ? applicable lcd duty : 1/64 to 1/256 ? the bias voltage can be supplied externally. ? lcd outputs : 160 ? a power-save function to reduce power consumption in a large-screen lcd panel. ? a 4-bit parallel data transfer to reduces its transfer speed to 1/4 of conventional serial transfer, providing low power consumption. ? data transfer clock frequency : 6.5 mhz (v dd =4.5 v) 4.0 mhz (v dd =2.7 v) ? 35mm-wide-film tcp tin-plating user area : 8 mm ? semiconductor MSM6779 160-dot segment driver (tcp) e2b0026-27-y2 this version: nov. 1997 previous version: mar. 1996
MSM6779 ? semiconductor 2/9 block diagram 160-dot 4-level driver 160-bit level shifter 160-bit latch (ii) 20-bit shift register control circuit data control 160-bit latch (i) (4x40) v 1l v 3l df load dispoff cp eio 1 v dd v ss v 4l v eel v 1r v dd v ee ? v dd v ss ? v 3r v 4r v eer eio 2 d 0 shl d 1 d 2 d 3 o 3 o 2 o 1 o 160 o 159 o 158
MSM6779 ? semiconductor 3/9 pin configuration (top view) v 1r v 3r v 4r v eer v ddr shl v ss eio 2 d 0 d 1 d 2 d 3 cp load df dispoff eio 1 v ddl v eel v 4l v 3l v 1l o 160 o 159 o 158 o 3 o 2 o 1 note: the drawing shown does not specify the exact outline of the tcp; it only specifies the pin layout.
MSM6779 ? semiconductor 4/9 absolute maximum ratings parameter symbol condition rating unit supply voltage (1) v dd ta=25?c C0.3 to 6.5 v supply voltage (2) v dd C v ee *1 ta=25?c 0 to 30 v input voltage v i ta=25?c C0.3 to v dd + 0.3 v storage temperature t stg C30 to +85 ?c *1 v 1 >v 3 >v 4 >v ee , v dd 3 v 1 >v 3 3 v dd C10 v, v ee +10 v 3 v 4 >v ee v 1 =v 1l =v 1r, v 3 =v 3l =v 3r , v 4 =v 4l =v 4r , v ee =v eel =v eer recommended operating conditions *1 v 1 >v 3 >v 4 >v ee , v dd 3 v 1 >v 3 3 v dd C7 v, v ee +7 v 3 v 4 >v ee v 1 =v 1l =v 1r , v 3 =v 3l =v 3r , v 4 =v 4l =v 4r , v ee =v eel =v eer note: unlike mold packages, tcp has a low light resistance. therefore, they are protected from light. parameter symbol condition range unit supply voltage (1) v dd 2.7 to 5.5 v supply voltage (2) v dd C v ee *1 14 to 28 v operating temperature top C20 to +75 ?c
MSM6779 ? semiconductor 5/9 electrical characteristics dc characteristics parameter symbol condition min. typ. max. unit "h" level input voltage v ih *1 0.8 v dd v "l" level input voltage v il *1 0.2 v dd v "h" level input current i ih v i =v dd , v dd =5.5 v *1 1 m a "l" level input current i il v i =0 v, v dd =5.5 v *1 C1 m a "h" level output voltage v oh i o =C0.2 ma, v dd =2.7 v *2 v dd C0.4 v "l" level output voltage v ol i o =0.2 ma, v dd =2.7 v *2 0.4 v on resistance r on v dd Cv ee =25 v, v dd =2.7 v, i v n Cv o i =0.25 v *3 *4 1.5 3.0 k w (v dd = 2.7 v to 5.5 v, ta=C20 to +75?c) stand-by current consumption i dd sby f cp =4.0 mhz, v dd =3.0 v v dd Cv ee =25 v, no load *5 300 m a current consumption (1) i dd f cp =4.0 mhz, v dd =3.0 v v dd Cv ee =25 v, no load *6 1.5 ma current consumption (2) i ee f cp =4.0 mhz, v dd =3.0 v v dd Cv ee =25 v, no load *7 2.0 ma current consumption (3) i v f cp =4.0 mhz, v dd =3.0 v v dd Cv ee =25 v, no load *8 200 m a input capacitance c i f=1 mhz 5 pf *1 applicable to load, cp, d 0 ~d 3 , eio 1 , eio 2 , shl, df, dispoff pins *2 applicable to eio 1 , eio 2 pins *3 v n =v dd Cv ee , v 4 =14/16 (v dd Cv ee ), v 3 =2/16 (v dd Cv ee ), v dd =v 1 *4 applicable to o 1 ~o 160 pins *5 display data 1010.....f df = 45 hz, current from v dd to v ss when the display data is not fetching. *6 display data 1010.....f df = 45 hz, current from v dd to v ss when the display data is fetching. *7 display data 1010.....f df = 45 hz, current from v dd to v ee *8 display data 1010.....f df = 45 hz, current on v 1 , v 3 , and v 4 pins. v 1 =v il =v ir , v 3 =v 3l =v 3r , v 4 =v 4l =v 4r , v ee =v eel =v eer note: the above values are q uaranteed when tcp is p rotected from li g ht.
MSM6779 ? semiconductor 6/9 switching characteristics note: the above values are quaranteed when tcp is protected from light. parameter symbol condition min. typ. max. unit clock frequency f cp duty=50%, v dd =2.7 v 4.0 mhz clock pulse width t w1 90ns load pulse width t w2 110 ns clock pulse rise/fall time t r , t f 20ns eio 1 , eio 2 set-up time t esu 80ns eio 1 , eio 2 hold time t ehd 80ns data set-up time t dsu 80ns data hold time t dhd 65ns clock load time 1 t cl1 0ns clock load time 2 t cl2 100 ns load clock time 1 t lc1 100 ns load clock time 2 t lc2 100 ns propagation delay time t phl c l =15 pf 380 ns d 0 ~d 3 0.8 v dd 0.2 v dd cp t w1 t f t r t w1 t w1 0.8 v dd 0.8 v dd 0.8 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.2v dd 0.2 v dd 0.2 v dd 0.2 v dd load t f t r t dsu t dhd t phl t esu t ehd t cl2 t lc1 t cl1 t lc2 t w2 0.8 v dd cp load 1 2 38 39 40 41 eio 1 , eio 2 (output) eio 1 , eio 2 (input) (2.7 v dd <4.5 v, ta=C20 to +75?c)
MSM6779 ? semiconductor 7/9 switching characteristics parameter symbol condition min. typ. max. unit clock frequency f cp duty=50%, v dd =4.5 v 6.5 mhz clock pulse width t w1 56ns load pulse width t w2 70ns clock pulse rise/fall time t r , t f 20ns eio 1 , eio 2 set-up time t esu 50ns eio 1 , eio 2 hold time t ehd 50ns data set-up time t dsu 50ns data hold time t dhd 40ns (4.5 v dd 5.5 v, ta=C20 to +75?c) clock load time 1 t cl1 0ns clock load time 2 t cl2 65ns load clock time 1 t lc1 65ns load clock time 2 t lc2 65ns propagation delay time t phl c l =15 pf 236 ns d 0 ~d 3 0.8 v dd 0.2 v dd cp t w1 t f t r t w1 t w1 0.8 v dd 0.8 v dd 0.8 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.2 v dd 0.2 v dd 0.2 v dd 0.2 v dd load t f t r t dsu t dhd t phl t esu t ehd t cl2 t lc1 t cl1 t lc2 t w2 0.8 v dd cp load 1 2 38 39 40 41 eio 1 , eio 2 (output) eio 1 , eio 2 (input) note: the above values are quaranteed when tcp is protected from light.
MSM6779 ? semiconductor 8/9 functional description pin descriptions v dd , v ss power supply for the device. v dd is set to 2.7 v to 5.5 v. v ss is set to 0 v. v 1l , v 1r , v 3l , v 3r , v 4l , v 4r , v eel , v eer bias power supply for the lcd drive voltages. power supply should be v dd 3 v 1 >v 3 >v 4 >v ee . dispoff input for controlling the output level of o 1 to o 160 . the v 1 level is output from o 1 to o 160 pins during "l" level input. refer to truth table. df input for lcd drive wave form ac synchronization. o 1 ~o 160 lcd drive outputs that correspond to each bit of the latch (ii). depending on the combination of the contents of the latch (display data) and df signal, one of 4 levels (v 1 , v 3 , v 4 , v ee ) is output. refer to truth table. cp clock pulse input for display data reading. data is taken into the latch (i) at the falling edge of the clock pulse. use an even number for the clock number per line (the number of the clock pulses during the period from load input to the next load input). eio 1 , eio 2 chip select signal input/output. input/output are controlled by the shl input. if the shl input at "l"level,eio 1 is output and eio 2 is input. if the shl input is at "h" level,eio 1 is input and eio 2 is output. if the shl is at "l" level, the first eio 2 is fixed to "l"level,and the following eio 2 is connected to the preceding eio 1 . if the shl is at "h"level,the first eio 1 is fixed to "l" level, and the following eio 1 is connected to the preceding eio 2 as shown below. when shl is at "l" level when shl is at "h" level start data o 160 eio 2 eio 1 o 1 end data eio 2 eio 1 eio 2 end data o 160 eio 1 eio 1 o 1 start data eio 2 eio 1 eio 2
MSM6779 ? semiconductor 9/9 d 0 , d 1 , d 2 , d 3 these are display data inputs that input data with clock synchronization. the table below shows the relationship between the lcd output for the display data and dfs and the lcd. load this is an input to simultaneously output the display data of one line stored in the latch (i). at the falling edge, the data in the latch (i) is transferred to the latch (ii) end is output. shl input to select for display data reading direction. input of "l" level at vss level fetches data in the direction from o 160 to o 1 sequentially, while input of "h" level at v dd fetches data in the direction from o 1 to o 160 . the table below shows the relationship between read data and driver outputs (o 1 to o 160 ). truth table x : don't care notes on usage (when turning the power on or off) if a high voltage is applied to a lcd drive system while the logic supply is floating, over -current may destroy the device, because the voltage over the lcd drive system is high. follow the sequence below when turning the power on or off. power on : logic system on ? lcd drive system on, or both on power off : lcd drive system off ? logic system off, or both off display data df lcd lcd drive output l l off non-selection level (v 3 ) hl on selection level (v 1 ) l h off non-selection level (v 4 ) hh on selection level (v ee ) data input eio 2 eio 1 shl inputs outputs l numbers of the clock pulse 40 clocks 39 clocks 38 clocks ... 3 clocks 2 clocks 1 clocks d 0 o 1 o 5 o 9 ... o 149 o 153 o 157 d 1 o 2 o 6 o 10 ... o 150 o 154 o 158 d 2 o 3 o 7 o 11 ... o 151 o 155 o 159 d 3 o 4 o 8 o 12 ... o 152 o 156 o 160 d 0 o 160 o 156 o 152 ... o 12 o 8 o 4 d 1 o 159 o 155 o 151 ... o 11 o 7 o 3 d 2 o 158 o 154 o 150 ... o 10 o 6 o 2 d 3 o 157 o 153 o 149 ... o 9 o 5 o 1 outputs inputs h df display data dispoff driver output (0 1 ~0 160 ) llh v 3 lhh v 1 hlh v 4 hhh v ee xxl v 1
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